FIG. 1 contains a block diagram of a conventional memory system 10 having a plurality of memory devices M0-Mn, e.g., n=7, on a plurality of memory modules 12, 14, connected to a controller 16. Data signal lines DQ0-7, DQ8-15, . . . , DQ56-63 have multi-drop links, such that the memory devices share the data signal lines. The capacitive load of the data lines affects the operation speed of the memory system. For example, 8 SDRAM, 4DDR (double data rate), 2DDR2 operational configurations typically may be connected together to respective data signal lines. As the operating speed of such systems increases, it becomes important to reduce capacitive loading and stub of the data signal lines to avoid the degradation of operation speed introduced by the capacitive loading. Multiple module connector slots also require that connector pins be shared along the data signal lines. This creates discontinuity in the signal path, which also degrades performance.
The command/address (C/A) signal lines C/A0 and C/A1 also have multi-drop links, so that memory devices M0-Mn on the same module 12, 14 share the same C/A signal line. In general, 8 or 16 memory devices share a single C/A line, depending on the system bus speed. For higher bus speeds, 8 memory devices typically share a common C/A line.
At present, the speed of a C/A line is slower than that of a data DQ line because of the loading effects. For DDR operation, the C/A bus is being operated at single data rate (SDR), half of the DQ speed. For higher speed operation, it will also be important to reduce capacitive loading and stub of the C/A line.
For a high-speed memory system, i.e., a system operating at more than 2 Gbps, a point-to-point (PTP) link, as opposed to a multi-drop link, should be used to reduce capacitive loading and stub of each signal line to meet high-speed operational requirements. For a high-density memory system supporting the PTP link, a plurality of memory modules are needed to support the memory application such as server or networking, but each memory module comprising the PTP link should have an input/output I/O module tab for each signal line. This causes an increase in the number of tabs, making it difficult to design and produce a suitable memory module. An approach in a high-density memory system supporting PTP without increasing the number of module tabs is to use stacked memory or a more dense planar location of DRAM in a single memory module.
Furthermore, memory devices mounted on one memory module should have PTP links between them for high-speed operation. In this case, each memory device has an I/O pin for each signal. The C/A and data information should be conveyed to the next level of DRAM tied through the stacking or planar configuration. Further, if differential signaling for high-speed signaling is adapted to the PTP link, the number of I/O pins is doubled. As the number of I/O pins increases, the package size also increases, and signal routing between memories gets more complex. Also, to reduce the capacitive loading of the DRAM, a uni-directional bus is necessary to achieve a given speed requirement.
FIGS. 2A and 2B are schematic block diagrams of a conventional memory system 10 illustrating a PTP repeating link structure. The system 10 includes a host or controller 16 connected to a first memory device M1, which is connected to a second memory device M2. Each of the memory devices includes a receive from controller port RFC, a transmit to memory port TTD, a receive from memory port RFD and a transmit to controller port TTC. Each RFC port is linked to the host 16 or the TTD port of another memory device through N pins. Each TTD port is linked to an RFC port of another memory device through N pins. Each TTC port is linked with the host 16 or the RFD port of another memory device through M pins. Each RFD port is linked with the TTC port of another memory through M pins. It is noted that N may be the same as M, or they may be different. All signals in the system 10 are linked using PTP links. M1 is connected to the host 16 by way of a PTP link. Also, M2 is connected to M1 or the host 16 by way of a PTP link. M1 and M2 may be constructed using a planar structure or a stacked structure.
The memory system 10 includes a merged WR/CA signal line which includes the merging of write signals and the C/A signals, and a read data line (RD). It is noted that the WR data line may be separated from the C/A line and also may be merged with the read data line RD instead of the C/A line.
FIGS. 2A and 2B illustrate read operations for both memory devices M1 and M2. The solid line represents a read operation performed on M1, and the dashed line represents a read operation on M2. As shown in FIG. 2A, a read operation on M1 results in the C/A signal for the read operation being transmitted directly to the memory M1 and the read data from M1 being transmitted directly to the host 16. A read operation on M2 involves the C/A signal for the read operation being transmitted to M1 and then repeated by M1 to M2. The read data from M2 is transmitted to M1 and repeated by M1 to the host 16. In FIG. 2B, read operation on M2 involves the C/A signal for the read operation being transmitted to M1 and repeated to M2. The read data from M2 is transmitted from the M2 TTC port directly to the host 16. A read operation on M1 involves the C/A signal for the read operation being transmitted to M1. The read data from M1 is transmitted by M1 to M2 and is transmitted directly from the M2 TTC port to the host 16.
The difference between the procedures of FIGS. 2A and 2B is in the path of the read operation. In FIG. 2A, the read latency of M1 is shorter that that of M2, but, in FIG. 2B, the read latency of M1 and M2 is the same.
FIGS. 3A and 3B are schematic block diagrams of another conventional memory system 20 illustrating a PTP link structure. In this configuration, M1 and M2 are operated at the same time. As a result, each of the memories M1 and M2 outputs half of the read data, i.e., M/2, to the host 16. This configuration is useful when it is desirable to reduce the number of pins required to connect between DRAMs and between the DRAM and the host 16.
FIG. 4 contains a table that illustrates the number of pins required in a memory package for each of the memory system configurations of FIGS. 2A, 2B, 3A and 3B. Specifically, “A”, “B”, “C” and “D” refer to the memory systems of FIGS. 2A, 2B, 3A and 3B, respectively. In the table, “pin” refers to a ball in a ball grid array (BGA) package or a lead in a plastic package. The number of pins shown in the table includes only signal pins and excludes power pins and miscellaneous pins. Normally, a memory chip is manufactured to have the maximum number of pads to meet the connection requirements of all PTP links. This prevents the need to provide separate chips for different types of links. Also, the package should have the maximum superset number of pins to satisfy each link. Package size is typically determined by the number of pins on the package. That is, in general, the greater the number of pins, the larger the package size. A “type”, i.e., type A, B, C or D, defines the maximum number of pins for that type. Accordingly, referring to the table of FIG. 4, the maximum number of pins for a memory chip is 2(N+M).